In field effect transistors (hereinafter referred to as FETs) employing compound semiconductors, n type layers are usually used as active layers, such as channel layers. Hereinafter the channel is called an n layer. In addition, a layer disposed beneath the channel layer and containing a dopant impurity producing a conductivity type opposite the conductivity type of the channel layer, i.e., n type, is a p type layer. This p type layer is called a buried p layer.
In conventional planar type compound semiconductor FETs, in order to reduce the source resistance and the drain resistance and increase the transconductance, high dopant concentration layers (hereinafter referred to as n.sup.+ layers) having an n type dopant concentration higher than that of the n layer are arranged adjacent to both sides of the n layer directly under a gate electrode. Those n.sup.+ layers are produced by ion implantation using the gate electrode as a mask, i.e., self-alignedly with the gate electrode. Generally, a refractory metal is employed for the gate electrode because the substrate after the ion implantation is annealed to activate the implanted ions. In this structure, however, the capacitance between the gate electrode and the n.sup.+ layers becomes an obstacle to high-speed operation of the FET. In addition, when the gate length is less than 1.0 .mu.m, the short channel effect occurs. Therefore, in recent years, LDD (Lightly Doped Drain) FETs have been employed, in which intermediate dopant concentration layers (hereinafter referred to as n' layers) having a dopant concentration higher than the dopant concentration of the n layer and lower than the dopant concentration of the n.sup.+ layers are interposed between the n layer and the n.sup.+ layers. FIG. 25(a) shows an example of the prior art planar LDD-FET. In the figure, reference numeral 1 designates a compound semiconductor substrate. An n type channel layer 2 is disposed on a center part of the substrate 1. N' layers 3 are disposed at opposite sides of and in contact with the n layer 2. N.sup.+ layers 4 are disposed contacting the n' layers 3. A refractory metal gate electrode 5a is disposed on the n layer 2, and ohmic electrodes 7a and 7b are disposed on the n.sup.+ layers 4. Reference numeral 6 designates an insulating film.
FIGS. 26(a)-26(g) illustrate process steps in a method of fabricating the LDD-FET shown in FIG. 25(a).
Initially, as illustrated in FIG. 26(a), a resist pattern 10 is formed on the compound semiconductor substrate 1. Using the resist pattern 10 as a mask, n type dopant ions are implanted into the substrate to a prescribed depth, forming an n layer 2. The pinch-off voltage V.sub.p of the FET is controlled by the implanted depth that depends on the accelerating energy and the dose. For example, when Si ions are implanted at an accelerating energy of 70 keV and a dose of 7.times.10.sup.12 cm.sup.-2, the pinch-off voltage V.sub.p is -2.0 V.
In the step of FIG. 26(b), after removal of the resist pattern 10, a thin refractory metal film 5 is deposited on the substrate, and a gate pattern 11 comprising a resist is formed on a portion of the refractory metal film 5. Preferably, WSi, WSiN, WN, or TiW is employed as the thin refractory metal film 5 as described in Japanese Published Patent Application No. Sho. 63-142681.
In the step of FIG. 26(c), using the resist pattern 11 as a mask, the thin refractory metal film 5 is etched by reactive ion etching (hereinafter referred to as RIE), forming a gate electrode 5a. When a gas mixture of CF.sub.4 +O.sub.2 or SF.sub.6 +CHF.sub.3 is employed for the RIE, the refractory metal film 5 is vertically etched without pattern-shifting from the resist pattern 11.
In the step of FIG. 26(d), after removal of the resist pattern 11, a resist pattern 12 is formed on the substrate. Using the resist pattern 12 and the refractory metal gate electrode 5a as masks, ion implantation is carried out to form the n' layers 3. The depth of the n' layers 3 from the surface of the substrate is approximately equal to the depth of the n layer 2.
After removal of the resist pattern 12, as illustrated in FIG. 26(e), an insulating film 13 is deposited on the substrate and etched back leaving portions on the both sides of the refractory metal gate electrode 5a. Hereinafter, the left portions 13 are called side walls. Preferably, an SiO.sub.2 film is used as the insulating film 13, and the etchback is carried out by RIE using a gas mixture of CHF.sub.3 +O.sub.2.
Thereafter, as illustrated in FIG. 26(f), a resist pattern 14 is formed on the substrate and, using the resist pattern 14, the refractory metal gate electrode 5a, and the side walls 13 as masks, ion implantation for producing the n.sup.+ layers 4 is carried out. The depth of the n.sup.+ layers 4 is approximately equal to the depth of the n layer 2.
After removal of the resist pattern 14 and the side walls 13, annealing is performed at about 800.degree. C. to activate the ions in the n layer 2, the n' layers 3, and the n.sup.+ layers 4. Finally, the insulating film 6 and the source and drain ohmic electrodes 7a and 7b are produced to complete the structure shown in FIG. 26(g). The annealing may be performed twice, i.e., first annealing for activating the n layer 2 and second annealing for activating the n' and n.sup.+ layers 3 and 4. In the step of implanting the n type dopant shown in FIG. 26(a), not only the n type dopant but also a p type dopant may be implanted to a depth exceeding the depth of the n layer 2 to form a buried p layer 31 under the active layers 2, 3, and 4 as shown in FIG. 25(b). This buried p layer 31 suppresses the short channel effect in an FET having a gate length less than 1.0 .mu.m. An FET having such structure is described by M. Noda et al. in IEEE Transactions on Electron Devices, Vol. 39 (1992), p.757. This FET is called a buried p layer LDD-FET (hereinafter referred to as BPLDD-FET). In this structure, the depletion layer is thinner at the interface between the n.sup.+ layer 4 and the buried p layer 31 than at interface between the n layer 2 and the buried p layer 31. Likewise, the capacitance is larger at the former interface than at the latter interface. Although the buried p layer 31 under the n.sup.+ layer 4 does not contribute to suppressing the short-channel effect, the capacitance at the interface between the p layer 31 and the n.sup.+ layer 4 reduces the operating speed of the FET. So, the buried p layer 31 may be produced by implanting the p type dopant after masking the n.sup.+ layers 4 with a resist pattern to prevent the p type dopant from being implanted into regions under the n.sup.+ layers. In this case, however, the resist pattern is not formed self-alignedly with the n.sup.+ layers 4.
In the FET fabricated as described above, since ion implantation is employed for the formation of the n layer 2, the controllability of the pinch-off voltage V.sub.p is good. In addition, since the gate electrode 5a comprises a refractory metal, the reliability of the contact between the gate electrode 5a and the n layer 2 is high. However, since current flows in the vicinity of the surface of the active layer, the drain breakdown voltage is low.
Meanwhile, FIG. 27 shows another example of a prior art compound semiconductor FET disclosed by B. Turner in Gallium Arsenide edited by M. J. Howes and D. V. Morgat, 1985, John Wiley & Sons Ltd, Chapter 10, p.377. This FET comprises a compound semiconductor substrate 1, an n layer 2 disposed on the substrate 1, an n.sup.+ layer 4 disposed on the n layer 2, a recess having a bottom within the n layer 2, and a low resistance metal gate electrode 8 disposed in the recess, and ohmic electrodes 7a and 7b disposed on the n.sup.+ layer 4 at opposite sides of the gate electrode 8.
A fabricating method of the FET with the recess structure shown in FIG. 27 is illustrated in FIGS. 28(a)-28(c). Initially, as illustrated in FIG. 28(a), on the compound semiconductor substrate 1 having the n layer 2 and the n.sup.+ layer 4, the ohmic electrodes 7a and 7b are produced contacting the n.sup.+ layer 4. Then, a resist film 17 having a prescribed opening pattern is formed on the substrate.
Thereafter, as shown in FIG. 28(b), using the resist film 17 as a mask, the n.sup.+ layer 4 and the n layer 2 are wet-etched with tartaric acid to form a recess, followed by deposition of a low resistance metal film 8. Preferably, Ti/Au or Ti/Al is employed for the low resistance metal film 8.
In the step of FIG. 28(c), the resist film 17 is dissolved with an organic solvent to lift-off unnecessary portions of the low resistance metal film 8 on the resist film 17, thereby producing the low resistance metal gate electrode 8. Since the same resist pattern 17 is used for the formation of the recess and the formation of the gate electrode, the gate electrode is formed self-alignedly with the recess.
In the FET with the recess structure fabricated as described above, current flows in a deeper region in the active layer than in the above-described BPLDD-FET, so that current concentration at the drain edge is reduced and the drain breakdown voltage is high. However, since it is difficult to accurately control the etching of the recess, the controllability of the pinch-off voltage V.sub.p is poor. In addition, since the gate electrode 8a comprises a low resistance metal, the reliability of the contact between the gate electrode and the n layer is low as compared to the FET employing the refractory metal gate electrode. In the structure shown in FIG. 27, the gate length is determined by the width of the opening of the resist film 17.
As described above, when a low resistance metal is used for the gate electrode, the reliability of the contact between the gate electrode and the n layer is not satisfactory. The reliability of the contact can be improved by a gate electrode having a double-layer structure in which a low resistance metal gate is disposed on a refractory metal gate. A compound semiconductor FET having such gate structure is disclosed by I. Hanyu et al. in Electronics Letters, Vol. 24 (1988), p.1327. FIG. 29 shows the FET structure. This FET comprises a compound semiconductor substrate 1, an n layer 2 disposed on the substrate 1, an n.sup.+ layer 4 disposed on the n layer 2, a recessed gate electrode comprising a refractory metal layer 5 and a low resistance metal layer 8, ohmic electrodes 7a and 7b disposed on the n.sup.+ layer 4 at opposite sides of the gate electrode, and an insulating film 6 covering the surface of the structure except upper surfaces of the ohmic electrodes 7a and 7b. Reference numeral 70 designates a porous portion of the refractory metal layer 5. Although in the above-described literature the n layer 2 has a double-layer structure of AlGaAs/GaAs, since the structure of the n layer matters little to the description about the structure and fabricating process of the gate electrode, a single n layer will be used in the following description.
FIGS. 30(a)-30(h) illustrate process steps in a method of fabricating the FET having the gate electrode with the double-layer structure comprising a refractory metal and a low resistance metal. Initially, a compound semiconductor substrate on which an n layer 2 and an n.sup.+ layer 4 are produced by epitaxial growth or ion implantation is prepared. As illustrated in FIG. 30(a), an insulating film 18 is deposited on the substrate and a resist film 19 having a desired opening pattern is formed on the insulating film 18. Thereafter, as illustrated in FIG. 30(b), using the resist film 19 as a mask, the insulating film 18 is etched and, subsequently, the n.sup.+ layer 4 and the n layer 2 are etched to form a recess. This etching is stopped within the n layer 2. When the insulating film 18 comprises SiO.sub.2, it is etched by RIE with a gas mixture of CHF.sub.3 +O.sub.2. The n.sup.+ layer 4 and the n layer 2 are etched by plasma etching with Cl.sub.2 or wet etching with tartaric acid.
In the step of FIG. 30(c), after removal of the resist film 19, an insulating film 20 is deposited over the substrate. The gate length is determined by the thickness of the insulating film 20 and the width of the opening pattern of the resist film 19. Thereafter, as illustrated in FIG. 30(d), the insulating film 20 is etched back, leaving portions on the inner side surfaces of the recess. Then, as illustrated in FIG. 30(e), a refractory metal film 5 comprising, for example, WSi, WSiN, or WN, is deposited by sputtering or the like, followed by annealing. After the annealing, a low resistance metal film 8 comprising, for example, Au, is deposited. Since the refractory metal film 5 is formed by sputtering of WSi, WSiN, or WN, the underlying n layer 2 is damaged. Therefore, annealing is required before the deposition of the low resistance metal film 8. This annealing is performed at 400.degree.-500.degree. C. Further, the refractory metal film 5 has porous portions 70 shown by dotted lines in FIG. 30(e) because of the difference in level, i.e., steps, on the substrate.
Thereafter, as shown in FIG. 30(f), a resist pattern 21 is formed on the low resistance metal film 8 and, using this resist pattern 21 as a mask, the low resistance metal film 8 is etched by ion milling with Ar gas and the refractory metal film 21 is etched by RIE with a gas mixture of CF.sub.4 +O.sub.2 or CHF.sub.3 +SF.sub.6. Further, as illustrated in FIG. 30(g), the resist pattern 21, the insulating film 18, and the insulating film 20 are removed, and source and drain ohmic electrodes 7a and 7b are formed on the n.sup.+ layer 4 at opposite sides of the gate electrode. Finally, as illustrated in FIG. 30(h), an insulating film 6 is deposited over the entire surface and portions of the insulating film 6 on the ohmic electrodes 7 are etched away. The gate electrode has a V-shaped hollow in the center of the top surface. Also in this fabricating process, the gate electrode is produced self-alignedly with the recess.
In the FET fabricated as described above, because the recess structure is employed, a high drain breakdown voltage is realized. In addition, the refractory metal layer 5 of the gate electrode is in contact with the n layer 2, so the reliability of the contact between the gate electrode and the n layer is high. However, since the recess is formed by etching, it is difficult to accurately control the pinch-off voltage V.sub.p. Further, since the refractory metal layer 5 of the gate electrode includes the porous portion 70 shown by the dotted line in FIG. 29, there is a possibility of abnormal diffusion of the low resistance metal layer 8 into the refractory metal layer 5.
FIG. 31 shows a prior art FET combining advantages of both the planar LDD-FET and the recessed gate FET, i.e., an FET providing high breakdown voltage, high reliability, and high V.sub.p controllability. In this FET, a gate electrode 5a is disposed in a recess while active layers 2, 3, and 4 are in an LDD structure.
FIGS. 32(a)-32(h) illustrate process steps in a method of fabricating the FET shown in FIG. 31. Initially, a recess is formed in a compound semiconductor substrate 1 using an etching technique with a resist mask 25. The process steps after the formation of the recess (FIGS. 32(c)-32(h)) are identical to the fabricating process of the LDD-FET already described with respect to FIGS. 26(a)-26(g). However, in the FET fabricated by this method, in contrast to the recessed gate FETs fabricated by the above-described methods shown in FIGS. 28(a)-28(c) and FIGS. 30(a)-30(h), since the gate electrode is not formed self-alignedly with the recess, the uniformity of the FET characteristics and their reproducibility are poor, so that good production yield is not obtained.
A description is given of a prior art method of fabricating a heterojunction bipolar transistor (hereinafter referred to as HBT). FIG. 33 is a sectional view of an HBT disclosed by N. Hayama and K. Honjo in IEEE Electron Device Letters, Vol. 11 (1990), p. 388. In this HBT structure, it is necessary to form an emitter electrode (E in the figure) self-alignedly with base electrodes (B in the figure), and the emitter electrode E is spaced apart from the base electrodes B using SiO.sub.2 side walls. A method of fabricating the HBT is illustrated in FIGS. 34(a)-34(i). Although a collector layer is not shown in the figures, it is included in the compound semiconductor substrate 1.
Initially, as illustrated in FIG. 34(a), a base layer 110 and an emitter layer 111 are epitaxially grown on the compound semiconductor substrate 1. Then, an SiN film is deposited over the emitter layer 111 and patterned by photolithography and etching to leave a portion 101 on a region where an emitter electrode is later produced.
In the step of FIG. 34(b), using the SiN film 101 as a mask, the structure is dry-etched using Cl.sub.2 gas until the etching front reaches into the emitter layer 111, forming a mesa structure for an emitter electrode. Thereafter, as illustrated in FIG. 34(c), an SiO.sub.2 film is deposited over the entire surface and etched back to form first SiO.sub.2 side walls 102 on both sides of the mesa structure. Further, portions of the emitter layer 111 outside the first side walls 102 are wet-etched until the surface of the base layer 110 is exposed.
In the step of FIG. 34(d), a base metal 103, such as AuMn, is deposited over the structure by vacuum evaporation. Then, as illustrated in FIG. 34(e), the base metal 103 is subjected to diagonal ion-milling to remove portions of the base metal 103 slightly deposited on the side surfaces of the SiO.sub.2 side walls 102. Thereafter, second SiO.sub.2 side walls 104 are formed in the same process as the first SiO.sub.2 side walls 102 as shown in FIG. 34(f).
In the step of FIG. 34(g), using the second side walls 104 as masks, the base metal 103 is etched by ion-milling, forming base electrodes 103a. Thereafter, as illustrated in FIG. 34(h), the SiN film 101 is selectively removed so as not to remove the first and second SiO.sub.2 side walls 102 and 104. This selective removal is easily carried out by plasma etching with SF.sub.6 gas. Finally, as illustrated in FIG. 34(i), an emitter electrode 105 is formed to complete the structure shown in FIG. 33.
In the above-described method, however, when the SiO.sub.2 film is etched back by RIE to form the SiO.sub.2 side walls, the substrate is damaged or undesirably etched, resulting in degradation in device characteristics and increased variations of the device characteristics. In addition, since diagonal ion-milling is used for removal of the base metal, the device characteristics are degraded as a result of imperfect etching with residual or excess etching.
According to the above-described prior art FETs, the planar LDD-FET employing a refractory metal gate (FIG. 25(a)) has a low drain breakdown voltage, and the recessed gate FET employing a refractory metal gate (FIG. 29) has a poorly controlled pinch-off voltage V.sub.p. Further, in the prior art FET employing both the recessed gate structure and the LDD structure in order to solve the above-described problems (FIG. 31), since the refractory metal gate is not self-aligned with the recess, good yield is not achieved. Furthermore, in the prior art BPLDD-FET employing a buried p layer for suppressing the short channel effect (FIG. 25(b)), although the buried p layer is desired to be absent under the n.sup.+ layer, in other words, present only under the n and n' layers, in order to remove the capacitance between the p layer and the n.sup.+ layers, since the buried p layer cannot be produced self-alignedly with the n.sup.+ layers, the capacitance between the buried p layer and the n.sup.+ layer remains, resulting in a reduction in the operating speed.
On the other hand, in the prior art HBT shown in FIG. 33, the RIE for forming the SiO.sub.2 side walls and the diagonal ion-milling for removing unnecessary portions of the base metal adversely affect the device characteristics and increase the variations in the device characteristics.